1. Field of the Invention
The invention relates in general to a test method and a test circuit for a memory, and more particularly, to a sector synchronized test method and circuit for a memory.
2. Description of the Related Art
FIG. 1 shows a schematic drawing of a wafer. As the semiconductor technique is more and more advanced, each die 102 of a wafer 100 comprises more and more transistor circuits. For example, the capacity of a memory becomes increasingly large. For a memory die such as erasable programmable or electrically erasable programmable memory die, the power consumption has to be reduced.
With regard to the erasable programmable or electrically erasable programmable memory, the yield test of the wafer has to be performed after completing the fabrication of integrated circuits. To perform the yield test on the wafer, or the IC test when the die is packaged as an IC, a DC test, a program and erase operation on the memory and a step of reading the data stored in the memory after the program and erase operation are required. From this, whether the die or the IC operates normally can be determined. Expressed as a mathematical formula as A*PT+B*PT−C*PT, A denotes the DC test time, B denotes the program and erase time, C denotes the read time, and PT means the probing times.
FIG. 2A shows a die, while FIG. 2B shows an IC. In the DC test, a direct current is input from the pad 204 of the die 202 or from the pin 208 of the IC 206 to test the open circuit status and short circuit status of the integrated circuit. A tester is used to input a test signal into the die 202 or the IC 206. The test signal determines the test mode, such as the program or the erase operation of the memory of the die 202 or the IC 206. After performing the program operation on the memory, the tester reads the data stored in the memory. After performing the erase operation on the memory, the tester reads the data stored in the memory again to confirm whether the program and erase operations performed on the die or IC are normal.
While performing the above test, the number of channels provided by the tester determines the quantity of dies or IC to be tested. If the number of dies or IC's of the wafer is large, many repetitions of program and erase operations are required with the fixed number of channels. Thus, the program and erase operations of the memory dominate the test time, which is proportional to the capacity of the memory. The early-developed memory has a capacity less than the current memory and takes about 20-30% of the test time for program and erase operations. The current memory has a much increased capacity, plus the requirement of low power consumption of IC. The program and erase operation time is increased to about 50% of the test time. With the fixed number of dies or IC's, the time required for DC test and reading the data stored in the memory is constant. Thus, the more the capacity of the memory is, the longer time the program and erase operations take.